In modern semiconductor device applications, hundreds of individual devices may be packed onto a single small area of a semiconductor substrate, and many of these individual devices may need to be electrically isolated from one another. One method of accomplishing such isolation is to form a trenched isolation region between adjacent devices. Such trenched isolation region will generally comprise a trench or cavity formed within the substrate and filled with an insulative material, such as silicon dioxide.
Trench isolation regions are commonly divided into three categories: shallow trenches (trenches less than about 1 micron deep); moderate depth trenches (trenches of from about 1 to about 3 microns deep); and deep trenches (trenches greater than about 3 microns deep).
Prior art methods for forming trench structures are described with reference to FIGS. 1-7. Referring to FIG. 1, a semiconductor wafer fragment 10 is shown at a preliminary stage of a prior art processing sequence. Wafer fragment 10 comprises a semiconductive material 12 upon which is formed a layer of oxide 14, a layer of nitride 16, and a patterned layer of photoresist 18. Nitride layer 16 comprises an upper surface 17, upon which photoresist layer 18 is supported. Semiconductive material 12 commonly comprises monocrystalline silicon which is lightly doped with a conductivity enhancing dopant.
Referring to FIG. 2, patterned photoresist layer 18 is used as a mask for an etching process. During the etch, unmasked portions of nitride layer 16, oxide layer 14, and semiconductive material 12 are removed to form a trench 20 extending within the semiconductive material 12. Trench 20 has a periphery defined by a trench surface 22 of semiconductive material 12.
Referring to FIG. 3, photoresist layer 18 is removed. Subsequently, an oxide fill layer 24 is formed over nitride layer 16 and within trench 20.
Referring next to FIG. 4, layer 24 is removed, generally by an abrasion technique chemical-mechanical polishing (CMP), down to about upper surface 17 of nitride layer 16. Such polishing forms an oxide plug 26 within the semiconductor material 12, with oxide plug 26 having an upper surface 28 substantially co-extensive with upper surface 17 of nitride layer 16. Plug 26 also comprises sidewalls 33 and upper corners 34 where sidewalls 33 join upper surface 28. Ideally, upper surface 28 would be planarized during the above-discussed polishing of layer 24, and would therefore comprise a flat surface. Also ideally, corners 34 would comprise about a 90.degree. angle, and would therefore be substantially square. However, due to practical limitations of polishing processes, surface 28 is generally, and undesirably, downwardly concave instead of flat, and corners 34 are undesirably substantially less than 90.degree., as shown. Prior art techniques have been developed to avoid such concavity and non-square corners.
One such prior art technique is discussed with reference to FIGS. 5-7. Referring first to FIG. 5, a prior art processing step subsequent to FIG. 2 is illustrated. Like numerals from the FIGS. 3 and 4 embodiment are utilized where appropriate, with differences being indicated by the suffix "a" or with different numerals. As with the above-discussed process of FIG. 3, oxide fill layer 24 is formed over nitride layer 16 and within trench 20. However, unlike the FIG. 3 processing step, a patterned photoresist block 30 is provided over trench 20 through an additional masking step not utilized in the FIG. 3 process.
Subsequently, as shown in FIG. 6, a portion of oxide layer 24 is removed to form an elevated step 32 of oxide material beneath the photoresist block 30.
Referring next to FIG. 7, photoresist block 30 is removed and oxide layer 24 subsequently polished. During the polishing, elevated step 32 compensates for the over-polishing which had previously formed a concavity in surface 28. Accordingly, resulting oxide plug 26a has a flat surface 28a and substantially square corners 34a, as shown. Preferably, flat surface 28a is substantially co-extensive with upper surface 17 of nitride layer 16.
After oxide plug 26a is formed, nitride layer 16 is removed to form a trenched isolation region 38. Such is illustrated in FIG. 8. The removal of nitride layer 16 is typically accomplished with a wet etch. Undesirably during such removal of layer 16, corners 34a are recessed to form the shown inwardly concave corners 36. Such recessed corners 36 can undesirably allow current leakage past the field isolation region 38, thereby substantially diminishing the effectiveness of isolation region 38 for electrically isolating adjacent devices.
For the above-described reasons, it is desirable to develop an improved process of forming a field isolation region, and to thereby form an improved field isolation region construction. Also, it would be desirable to develop a method of forming a field isolation region with a substantially flat upper surface, without the requirement of the extra masking step required to form photoresist block 30 of FIG. 5.